The disclosed invention is generally directed to time delay circuits, and is more particularly directed to a digital time delay circuit which does not utilize extensive shift register circuits, and further does not utilize high speed memory devices.
Time delay circuits are utilized to provide a delayed replica of a time varying signal, and are utilized in various types of signal processing including, for example, radar systems.
Known time delay circuits have included extensive banks of shift register circuitry for transferring data from one stage to another, where the number of stages is determined by the maximum delay required. It is well understood that the use of shift register time delay circuitry involves considerable circuitry when the required delays are large, which further results in greater power consumption.
Other known circuitry include high speed memory systems that continuously store the value of the input for later output. High speed memory, however, tends to be expensive, and large amounts of memory would be required for longer delays.
A further consideration with known time delay circuits is the difficulty in changing the delay provided.